1. Field of the Invention
The present invention relates to an apparatus for and a method of inspecting a semiconductor integrated circuit.
2. Description of the Related Art
The following technique disclosed in Japanese Patent Publication No.6-103171 is known as a conventional apparatus for inspecting a semiconductor integrated circuit. As shown in FIG. 1, a laser beam 2 emitted by a laser oscillator 1 is inputted through a light collecting lens 3 to a scanner 4. The scanner 4 has a function of converting the collected laser beam into slit light through a cylindrical lens and the like and then deviating the slit light through a galvanomirror and the like. Thus, this apparatus is complex and expensive.
A slit light 5 outputted by the scanner 4 is emitted to a target body 6. This target body 6 is photographed by a CCD camera 7. A picture signal outputted by the CCD camera 7 is converted into a one-bit digital picture signal by an A/D converter 8. A picture signal outputted by the A/D converter 8 is stored in a picture memory 9 in accordance with an instruction from a CPU 12, and it is simultaneously inputted to an address detecting circuit 11, which detects an address when picture information is maximum for each horizontal scan.
FIG. 2 shows the content of the picture memory 9. As shown in FIG. 2, in horizontal h pixels and vertical v pixels, each pixel is configured at one bit. An address in a horizontal direction is represented by i (i=1 to h), and an address in a vertical direction is represented by j (j=1 to v). This picture memory 9 is configured such that visual information of the CCD camera 7 is arrayed as two dimensions, and it corresponds to each CCD element.
In the above-mentioned explanation, the target body 6 may be BGA (Ball Grid Array) or CSP (Chip Size Package).
As shown in FIGS. 3A, 3B, the BGA is configured such that connection units (gold pads) are aligned on a mount surface 51a of an IC chip 51 longitudinally and laterally, and solder balls 52, 53 . . . are placed on the respective connection units. In this BGA, the solder balls 52, 53 . . . aligned on the mount surface 51a of the IC chip 51 are fused and bonded on lands of a substrate, and the surface mounting operation is carried out.
Also, the CSP is configured such that a plurality of solder balls are aligned on the mount surface of the IC chip longitudinally and laterally, similarly to the BGA. As shown in FIG. 4, the CSP is configured so as to be sealed by a resin mold 62 in the size substantially similar to that of an IC chip 61 (real chip size package) and solder balls 63, 64 . . . are placed through respective bumps B on the connection units of the IC chip 61. In this CSP, similarly to the BGA, the solder balls 63, 64 . . . aligned on a mount surface 61a of the IC chip 61 are fused and bonded on the lands of the substrate, and the surface mounting operation is carried out.
As mentioned above, when the plurality of solder balls are placed on the mount surface of the IC chip and those solder balls are used to carry out the surface mounting operation, the connection units of the IC chip are typically composed of one row or two or more rows. Thus, the solder balls are placed in a shape of rows.
A light cutting method used to measure a cubic body, such as a solder ball or the like, will be described below.
As shown in FIG. 5, a plurality of BGA type IC chips 102 are placed on a JEDEC tray 101. The IC chip 102 is set such that its mount surface 102a is located uprightly. A plurality of solder balls 103 aligned on the mount surface 102a longitudinally and laterally are inspected.
The inspection of the solder ball 103 includes the inspections of a shape, a height, a solder amount (ball volume), a position and a coplanarity of a bump.
The coplanarity typically implies a floating amount of a terminal from a ground that is formed by a package terminal. It is represented by a distance between each terminal when a surface mount package is placed on a flat plane and the mount plane. If this distance is too long, it is impossible to sufficiently fill solder between the terminal and a foot print of a mount substrate when the surface mounting operation is done. Thus, there may be a case that the solder bonding is imperfect. The coplanarity is the dimension, from which the reliability and the yield of the solder boding is determined, in the package on which the surface mounting operation is performed. In particular, a value at which the distance between each terminal and the mounted plane is maximum is important.
In the BGA representing an area array package, the yield in the size of the solder ball forming the sealant of the package and the curvature and the terminal of the substrate has influence on the coplanarity. In order to inspect the coplanarity of the IC chip, as a rule, it is necessary to measure the heights of all solder balls in the IC chip.
A linear light emitter 104 obliquely emits a linear light L to the mount surface 102a of the IC chip 102. The linear light L scans the solder balls 103 for each row. The linear light emitter 104 is designed so as to carry out a reciprocating motion in order to scan the mount surface 102a of the IC chip 102 through the linear light L. Thus, as shown in FIG. 6, the linear light L obliquely emitted to the mount surface 102a of the IC chip 102 by the linear light emitter 104 is scanned in an X-direction indicated by an arrow in FIG. 6, along the mount surface 102a. 
Here, the linear light L may be, for example, a laser light. Also, the linear light L may be the lights in which the lights emitted from a light source, such as a light emission diode (LED) or the like, are converged through a cylindrical lens into linear lights.
As shown in FIG. 5, a photographing unit 105 for photographing a changing picture of the linear light L is placed directly over the mount surface 102a of the IC chip 102 so that it is located opposite to the mount surface 102a. The photographing unit 105 is, for example, the CCD camera. The photographing unit 105 is fixed.
The photographing unit 105 is fixed, and it is not shifted together with the scanning (the arrow X of FIG. 6) of the linear light L. Thus, as shown in FIG. 6, the photographing unit 105 has the photographing range in which when the linear light L is scanned in the X-direction along the mount surface 102a and the light is emitted to the solder balls 103 in a plurality of rows, all of the solder balls 103 in the plurality of rows can be covered.
An operational process is performed on the picture information photographed by the photographing unit 105, and the heights of the respective solder balls 103 are detected. Here, for example, the following methods can be used in order to detect the heights of the respective solder balls 103, on the basis of the picture information of the photographing unit 105.
As shown in FIG. 7, if a distortion amount of the linear light L is assumed to be I and an emission angle of the linear light emitter 104 is assumed to be θ, a protrusion height h of each solder ball 103 is represented by h=I tan θ. The distortion amount I of the linear light L is changed in the process in which the linear light L scans the respective rows of the solder balls 103 in the plurality of rows.
As mentioned above, in the light cutting method, the linear light L is obliquely emitted to the mount surface 102a of the IC chip 102, and this linear light L is scanned on the mount surface 102a on which the solder balls 103 are placed. Then, the fact that the linear light L is distorted proportionally to the mount height (protrusion height h) of the solder ball 103 during the scanning is used to perform the operational process on the changing picture information of the linear light L, for example, by using the equation of h=I tan θ. Accordingly, the height of each solder ball 103 is measured.
Thus, it is possible to inspect the allowance or rejection of the plurality of solder balls 103 aligned on the mount surface 102a of the IC chip 102 easily and surely. In particular, it is possible to accurately measure the mount height h of the solder ball 103, and possible to provide this method for the inspection of the coplanarity.
By the way, Japanese Laid Open Patent Application (JP-A-Heisei 10-209227) discloses the following method of inspecting a semiconductor integrated circuit. In the method of inspecting a semiconductor integrated circuit, which inspects a plurality of solder balls aligned on a mount surface of a semiconductor integrated circuit longitudinally and laterally, a linear light emitter obliquely emits a linear light to the mount surface, and scans the solder balls for each row, and a photographing unit photographs a changing picture of the linear light during the scanning, and a picture processor performs an operational process on the photographed picture information, and then detects a height of each solder ball. The operational process of the picture process is carried out by using the equation represented by a protrusion height h=I tan θ, when a distortion amount of the linear light is assumed to be I and an emission angle is assumed to be θ.
Japanese Laid Open Patent Application (JP-A-Heisei 11-72316) discloses the following apparatus for measuring a flatness of an IC lead. This apparatus is provided with: a slit plate having a plurality of linear slits for light transmission, which are arrayed at an identical interval in parallel to each other; a parallel light flux light source for emitting a parallel light flux to the slit plate from the inclined direction at the same angle on an opposite side along the array direction of the linear slit with respect to a normal line of the slit plate; a work stage for holding an IC package targeted for the measurement at a position on a light emission side of the slit plate so that the formation plate of the lead ball is parallel to the slit plate; a photographing unit for photographing the surfaces of the respective lead balls arrayed on the lead ball formation plane; and a measuring unit for determining a distance between centers of light arrival points formed on the surfaces of the respective lead balls on the basis of the picture generated by the photographing unit and then measuring the flatness of each lead ball in accordance with the distance between the centers.
As mentioned above, in the light cutting method, the entire shape and size (height) of each bump are recognized on the basis of the distortion amount I and the emission angle θ of each linear light L, when the linear light L is emitted to a different height of each bump a plurality of times, in the process in which the linear light L scans each bump.
As mentioned above, the reason why a plurality of photograph pictures with regard to each bump are generated by emitting the linear light L to a plurality of positions at the different heights in each bump is that an apex position in the bump is not always known in advance so as to determine the height of the entire bump.
That is, the maximum value of the heights obtained from each of the plurality of photograph screens with regard to each bump is assumed to be the height of the entire bump.
In this way, it is necessary to perform the photographing operation on each bump a plurality of times. Thus, in order to make the measuring time shorter, a time required to carry out each photographing operation (a time required to obtain one picture) is desired to be shorter.